In the semiconductor industry, there is a constant demand to increase the operating speed of integrated circuits (ICs). This increased demand is fueled by the need for electronic devices such as computers to operate at increasingly greater speeds. The demand for increased speed, in turn, has resulted in a continual size reduction (i.e., compactness) of the semiconductor devices. Specifically, the channel length, junction depths, and/or gate dielectric thickness of field effect transistors (FETs) are reduced to provide a compact semiconductor structure.
Thus, there is a constant drive to reduce the size, or scale, of the components of a typical FET to increase the overall speed of the FET. Additionally, reducing the size, or scale, of the components of a typical FET also increases the density and number of FETs that can be fabricated on a given single semiconductor wafer.
However, reducing the channel length of a transistor also increases short-channel effects. Short-channel effects include, among other things, an increased source/drain (S/D) leakage current when the transistor is switched “off”.
It is noted that short channel effects are relatively unimportant in long channel transistors. However, long channel FETs are generally difficult to fabricate into a compact structure since long channel FETs are restricted by the contact pitch.
In view of the above, there is a need to provide a semiconductor structure having a long channel length and/or wide-channel width without reduction in the design rule of the transistor. Moreover, a semiconductor structure including a long channel length and/or wide-channel width is needed within a fixed contact pitch without introducing shorting between the gate conductor and the source/drain contact regions. Furthermore, there is a need for providing a semiconductor structure including a long channel length and/or wide-channel width within a fixed contact pitch without decreasing the spacing between the source/drain contact region and the gate conductor and hence increasing the components of source/drain contact region-to-gate conductor coupling capacitance.